Hello, I'm
Designing novel architectures for energy-efficient AI at UW–Madison — from stochastic computing hardware to resilient NoC interconnects.
(psst — hover over any router in the mesh to break it, and watch the flits route around the fault)
↓Hello! I’m Paridhi, a PhD student and computer architecture researcher at the University of Wisconsin-Madison. Working in the STACS Lab under Prof. Joshua San Miguel, my research focuses on building the next generation of energy-efficient and resilient hardware. Currently, I spend most of my time exploring deadlock-free routing for 2.5D chiplet interconnects and designing stochastic processing units for low-power AI.
Beyond my academic research and industry time at Arm, I care deeply about building communities in engineering. Whether I am serving as the ECE Graduate Student Association Vice President or mentoring undergraduate students, I believe the best engineering happens when we learn and grow together
When I'm not simulating chips or eating them, you'll find me upcycling thrifted clothing into new pieces, hiking, or cooking something new in my perpetually-too-small kitchen.
Drinking: boba · Simulating: … cycles in gem5
Low-Power AI
Designing the Stochastic Processing Unit (SPU) — a specialized architecture that computes on probabilistic bitstreams to run AI workloads at a fraction of the power — and building its open-source simulator so other researchers can experiment with it.
Interconnects
Investigating and designing advanced routing techniques to guarantee deadlock freedom across 2.5D integrated-circuit interconnects. By rethinking multi-die data flow, this work aims to create highly resilient, scalable chiplet architectures. Validated through extensive gem5 system architecture simulations.
P. Gupta, Z. Pan, H. Hsiao, and J. San Miguel, “SCoRe: Stochastic Compressed Representations,” in 3rd Workshop on Unary Computing (WUC), co-located with ASPLOS '26, Mar. 2026.
R. Selagamsetty, P. Gupta, W. Li, J. S. Miguel, and M. Lipasti,“ gem5 Support for Pseudo-Random Number Generation, in Proc. gem5 Workshop (ISCA),” Raleigh, NC, USA, Jun. 2026
Arm — Arizona
Brought up liveness properties for formal verification and enabled finer-grained testing by modularizing verification interfaces.
Arm — Arizona
Leveraged LLMs for CPU performance modeling: built a RAG pipeline over internal design data, automated it with Jenkins, and improved answer accuracy by 37%.
Mindtickle — Pune, India
Built LLM prompts that turn sales-call transcripts into follow-up emails, action items, and call scores; benchmarked GPT service providers and cut latency by 10%.
Digital System Fundamentals, UW–Madison
Teaching as the David & Sarah Epstein Teaching Fellow.
ECE-SPARK & undergraduate research
Mentored two ECE-SPARK students in Summer 2026 and have been mentoring an undergraduate researcher since December 2025.
ECE 552 & ECE 252, UW–Madison
In-class peer coach for Intro to Computer Architecture (ECE 552) and Intro to Computer Engineering (ECE 252); undergraduate student assistant for ECE 252.
Awarded the David & Sarah Epstein Teaching Fellowship for Fall 2026.
Elected Vice President of the ECE Graduate Student Association (2026–27 term).
Received the ECE Graduate Student Award for Excellence in Service.
Presented “SCoRe: Stochastic Compressed Representations” at the 3rd Workshop on Unary Computing (WUC), co-located with ASPLOS '26.
Began my PhD at UW–Madison, supported by the ECE Distinguished Graduate Fellowship.
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